1. Field of the Invention
The present invention relates to a semiconductor device with a structure that element isolation regions are formed so as to be self-aligned with gate electrodes and a method of manufacturing the same.
2. Description of the Related Art
With recent reduction in the design rules, semiconductor devices have employed a structure that element isolation regions are formed so as to be self-aligned with gate electrodes. As one of such semiconductors, JP-A-2003-78047 discloses a NAND flash memory. The disclosed NAND flash memory is manufactured as follows. A first insulating film serving as a gate insulating film is formed on a principal surface of a semiconductor substrate. A first electrode layer (corresponding to an electrode layer) serving as a floating gate electrode is formed on the first insulating film. Subsequently, the first electrode layer, first insulating film and a flat part of the semiconductor substrate are selectively removed so that element isolation trenches are formed. Next, an insulating film (corresponding to a second insulating film) is buried in the element isolation trenches so that element isolation insulating films are formed, respectively. The element isolation insulating film is etched until a part of the element isolation insulating film is located at a level between the first electrode layer and the first insulating film. Subsequently, a second insulating film (corresponding to a third insulating film) is formed as an interpoly insulating film so as to cover the whole first electrode layer and the whole element isolation insulating film.
Subsequently, a second electrode layer (corresponding to a conductive layer and a low resistivity metal film) is formed on the second insulating film. A gate processing pattern is formed on the second electrode layer. The second electrode layer, the second insulating film and the first electrode layer are removed with the gate processing pattern serving as a mask. In this case, since an upper part of the insulating film formed in the element isolation region has previously been etched so as to be nearly at the level of an upper surface of the first insulating film, etching residue can be suppressed with respect to the first electrode layer on the sidewalls of the second insulating film, occurrence of short circuit can be suppressed between gate electrodes.
In the above-described method, however, sidewalls of the first and second electrode layers are exposed when the upper part of the second insulating film is etched so as to be nearly at the level of an upper surface of the first insulating film. Accordingly, there is a possibility that electrical characteristics of the first and second electrode layers may be deteriorated. In particular, the possibility of deterioration becomes higher when these electrode layers contain a low resistivity metal film.